1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate and the liquid crystal display device including the same.
2. Discussion of the Related Art
A cathode ray tube has been widely used as a display device such as a television and a computer monitor. However, the cathode ray tube has a large size, heavy weight, and high driving voltage. Therefore, flat panel displays that are thin, light weight, and low in power consumption have been in demand. Among these devices, the liquid crystal display (LCD) device has been widely developed because of its superior resolution, color image display, and image quality.
The LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The LCD device displays images by using differences in refractive indices of light due to the anisotropy of liquid crystal.
An LCD device including thin film transistors and pixel electrodes of a matrix form, which is referred to as an active matrix LCD (AM-LCD) device, is widely used due to its high resolution and fast moving images. In the AM-LCD device, the thin film transistor functions as a switching element that controls voltage applied to the liquid crystal layer in a pixel and changes the transmittance of light in the pixel.
The thin film transistor for the AM-LCD device will be described in detail with reference to the attached drawings.
FIG. 1 is a schematic plan view of an array substrate for a liquid crystal display device according to the related art and shows a thin film transistor as a main part. As shown in FIG. 1, a gate line 10, is formed in a first direction and a data line 40, crossing the gate line 10 is formed in a second direction to define a pixel area. A gate electrode 12 is connected to the gate line 10, and an active layer 30, which is made of amorphous silicon, is formed on the gate electrode 12. Although not shown in the figure, a gate insulating layer is formed between the gate electrode 12 and the active layer 30. A source electrode 42a, which is connected to the data line 40, overlaps the edge of the active layer 30 in part and a drain electrode 42b, which is enclosed by the source electrode 42a, is disposed on a central portion of the active layer 30. The drain electrode 42b is connected to a drain extended portion 42c, which is formed in the pixel area. The gate electrode 12, the source electrode 42a and the drain electrode 42b constitute a thin film transistor.
A passivation layer (not shown) is formed on the source and drain electrodes 42a and 42b, and the passivation layer includes a drain contact hole 52 exposing the drain extended portion 42c. A pixel electrode 60 is formed on the passivation layer and is connected to the drain extended portion 42c through the drain contact hole 52.
In the thin film transistor, since the gate electrode 12 overlaps the source and drain electrodes 42a and 42b with definite widths, first and second parasitic capacitors Cgs and Cgd are formed.
When a channel is generated in the active layer 30 by voltage applied to the gate electrode 12, the thin film transistor functions as a switching element by permitting currents to flow through the channel. If the gate electrode 12 overlaps the source and drain electrodes 42a and 42b to form the parasitic capacitors Cgs and Cgd, many problems may occur because the parasitic capacitors Cgs and Cgd are connected to the gate electrode 12 in parallel. That is, the parasitic capacitors Cgs and Cgd may delay signals applied to the gate electrode 12 or may change the threshold voltage of the thin film transistor. Therefore, it is beneficial that values of the parasitic capacitors Cgs and Cgd are minimized.
The structure of the thin film transistor and the parasitic capacitors will be described in detail with reference to FIG. 2. FIG. 2 is a schematic cross-sectional view along the line II-II′ of FIG. 1.
As shown in FIG. 2, a gate electrode 12 is formed on a substrate 1 and a gate insulating layer 20 is formed on the entire surface of the substrate 1 covering the gate electrode 12. An active layer 30 of amorphous silicon is formed on the gate insulating layer 20 corresponding to the gate electrode 12. A source electrode 42a and a drain electrode 42b, which are facing and spaced apart from each other, are formed over the active layer 30. The source electrode 42a is connected to a data line 40 and the drain electrode 42b is connected to a drain extended portion 42c. As stated above, the gate electrode 12, the source electrode 42a and the drain electrode 42b constitute a thin film transistor.
A passivation layer 50 covering the source and drain electrodes 42a and 42b is formed on the entire surface of the substrate 1. The passivation layer 50 has a drain contact hole 52. A pixel electrode 60 is formed on the passivation layer 50 and is connected to the drain extended portion 42c. 
In the thin film transistor, the source and drain electrodes 42a and 42b overlap the gate electrode 12 in fixed portions, and the overlapping portions become first and second parasitic capacitors Cgs and Cgd, respectively. The first and second parasitic capacitors Cgs and Cgd negatively effect the characteristics of the thin film transistor and decrease the image quality of the liquid crystal display device. Thus, it is beneficial that values of the first and second parasitic capacitors Cgs and Cgd are minimized.
In addition, the drain electrode 42b may be misaligned with respect to the gate electrode 12 when the drain electrode 42b is formed. This means that a size of the drain electrode 42b overlapping the gate electrode 12 may change, and cause variation of the second parasitic capacitor Cgd.
More particularly, when misalignment occurs, a length l of the drain electrode 42b overlapping the gate electrode 12 may increase or decrease by Δl. Therefore, the size of the drain electrode 42b overlapping the gate electrode 12, and a parasitic capacitance Cpara of the second parasitic capacitor Cgd also includes a parasitic capacitance deviation ΔCpara, which may be a positive value or a negative value. The parasitic capacitance deviation ΔCpara may interfere with data signals that are applied to the pixel electrode 60 through the data line 40 and cause problems such as flicker to get worse.